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7 \4 P* f' k/ \
" Q, ~) n9 q+ @: @//----------------------------------------------------------------------------. V# T+ J3 A3 W+ U; U
// tft_lcd - module
$ Y6 J% O0 C. n [8 }. n//----------------------------------------------------------------------------
9 E" O& R& K' T+ W// IMPORTANT:& w4 i, h% }! I/ I A5 C: f
// DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. [: F- \, l* ~0 a( E
//
- s$ K$ l& C+ O2 q% E$ K// SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
( i4 W+ s: p( P% K% w7 m+ \//# x8 U+ E1 h: z Z+ f- F' y/ \
// TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
5 b& g! m- p+ V& m" `) ]// PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
# V a0 y5 |" I. j$ Z5 }. h// OF THE USER_LOGIC ENTITY.% O3 k0 p# o" z& O
//----------------------------------------------------------------------------
+ U C2 ~. o* Z3 b5 G8 `//
2 w: O: \# ^. \" I1 O' t+ [// ***************************************************************************
: Q; G! G! {8 N: E// ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **$ u, G4 ~& a; r
// ** **
# G7 l3 E) O+ o/ {/ U. b// ** Xilinx, Inc. **, |$ [ g5 t3 s/ f- [: e
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **5 Z! V& _) z# V" [4 { m
// ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **. V" ?- ?; x' K; q3 \) |7 b
// ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **4 |. r( Z+ U- r& T( ^3 H9 m- `
// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **+ ~- X. V$ g" g* F! a
// ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
, P4 a4 D+ S( L// ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
1 `/ l! H/ p, b// ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **0 H0 _' z' {% f
// ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
* ]# }1 Z: `/ ^3 C* A7 L1 ^// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
( {) C- O) T7 l9 [// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
+ h! [8 X6 e9 ]" x// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
9 K9 v8 X" M* H% h// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
& m4 b+ r& W& u5 F5 _5 g' t// ** FOR A PARTICULAR PURPOSE. **
0 G! O( @; L' i7 I) M' H// ** **% P1 d# ^' k k2 T6 E8 D
// ***************************************************************************$ r! o; e* e" C, h& Z7 R9 `/ P' Q+ |
//! v! ^; K9 W6 D: E9 ?
//----------------------------------------------------------------------------+ F3 j8 a: {; ]
// Filename: tft_lcd
( N3 T5 A: M. n4 W// Version: 1.00.a6 U0 z! M9 s- K+ F+ t. t+ V/ \. t
// Description: Example Axi Streaming core (Verilog).7 J4 |& H9 [$ u* E
// Date: Thu Oct 24 17:52:44 2019 (by Create and Import Peripheral Wizard)
( P. w; F- ^) U. y, a// Verilog Standard: Verilog-2001
7 j3 m5 u, X" R8 [//----------------------------------------------------------------------------, t e* i) n& S5 w3 R% Z
// Naming Conventions:
% A+ {/ ]0 ~& Q7 i) H2 o+ L// active low signals: "*_n"
' F& c+ @1 Z7 y/ y// clock signals: "clk", "clk_div#", "clk_#x"
& f) m5 D1 k& |$ E: p% F// reset signals: "rst", "rst_n"
# j: }2 k- q0 Q* k' j% _( q// generics: "C_*"( n4 I8 ]9 \8 V& v" D
// user defined types: "*_TYPE"
. D. {6 m* v& v; m4 q7 i: Q// state machine next state: "*_ns"
) \; H9 h3 u* r// state machine current state: "*_cs"
( h7 k7 N! j& O) \" z/ [// combinatorial signals: "*_com"
6 W. Q5 m3 ]$ n7 y0 n0 R+ |// pipelined or register delay signals: "*_d#"
% K$ Y: z' M5 |. ?* K+ j% Z// counter signals: "*cnt*"
0 h6 E! m3 x+ v, B// clock enable signals: "*_ce"
, I* j4 {# _1 ^+ W// internal version of output port: "*_i"
8 U% l( F0 b4 Q, t H1 ?// device pins: "*_pin"
' l$ o2 J' K+ h# ?// ports: "- Names begin with Uppercase"' y; ]3 H3 j6 c) g n) P' ~2 L: h: A
// processes: "*_PROCESS"0 x3 b2 c3 ~0 K- A$ p3 Q2 a
// component instantiations: "<ENTITY_>I_<#|FUNC>"
8 d# @1 E' }) f' d& X0 g. Z//----------------------------------------------------------------------------0 K/ b' [4 a) I+ Y2 p) O
' Y8 w: o& |% i& g' p1 j////////////////////////////////////////////////////////////////////////////////; h2 Q6 |. V Y$ z! ?6 d, C2 w) X
//& G7 S: @9 d0 `" [
//
& ^( f8 W6 B8 l0 H1 J! T! _// Definition of Ports
; D, n* P2 D, f6 j4 W G8 r l3 i// ACLK : Synchronous clock
' w- M: w7 [6 Y: j8 R8 g% ~// ARESETN : System reset, active low+ C$ a/ {5 w' s4 {
// S_AXIS_TREADY : Ready to accept data in
{6 p% g9 a: ?1 F, b3 k// S_AXIS_TDATA : Data in
$ b0 ^4 G5 D4 U7 D9 m1 ?/ M, k' J// S_AXIS_TLAST : Optional data in qualifier: \6 n3 H: x9 v
// S_AXIS_TVALID : Data in is valid% C ~3 J0 l) S- ]. X6 d
// M_AXIS_TVALID : Data out is valid
# j2 t# g. v. {6 Y// M_AXIS_TDATA : Data Out
/ P4 g H( j& Q$ _# ?. B/ z// M_AXIS_TLAST : Optional data out qualifier
. E. |2 H1 ]% I0 b, }2 K// M_AXIS_TREADY : Connected slave device is ready to accept data out( s* K, r+ v. }/ D/ I( e
//
1 ~4 s5 h2 ?! R" l3 l////////////////////////////////////////////////////////////////////////////////" u. b: t' H$ A$ L. k0 B
& `0 f0 }2 ?+ `/ G* `//----------------------------------------
3 w. u4 x5 v) X+ C, ?. Z t// Module Section
, J- ^- x5 X& ~" L/ U9 R3 I//----------------------------------------) O! @4 @0 ^, c' ^' c, c
module tft_lcd
: H# F- [/ h2 |4 s7 i7 u (4 \( s0 M# O; q& Z @8 s) ~
// ADD USER PORTS BELOW THIS LINE
& S+ {% }& u5 Y j6 Y% D. Z // -- USER ports added here 8 t3 H' G8 d1 ?' I/ `1 R# k! J
// ADD USER PORTS ABOVE THIS LINE 1 m/ b p. q7 K4 m9 u: a+ b7 f
( s4 d9 A8 W1 h) d1 `7 d // DO NOT EDIT BELOW THIS LINE ////////////////////8 _$ R: `) ` M ]( j
// Bus protocol ports, do not add or delete. 2 i Q9 y9 A) }4 V3 E
ACLK,
' u7 J8 v; x q4 J+ [; T ARESETN,
, Q, p# l8 h+ y8 d# W S_AXIS_TREADY,) o& L7 ~, P% T' a( S: N9 L9 i
S_AXIS_TDATA,, O* z, l. {& X6 U. M: C
S_AXIS_TLAST,2 A0 [5 {) @& y: h7 c( u( j7 d
S_AXIS_TVALID,
& V1 U* `1 c# I M_AXIS_TVALID,8 N8 N t4 t3 b. L
M_AXIS_TDATA,
3 R& ]6 W+ E, p& W4 x" ? M_AXIS_TLAST,; M4 Z& V4 y. t8 L3 d
M_AXIS_TREADY
' R% |9 K. y+ b/ G, p // DO NOT EDIT ABOVE THIS LINE ////////////////////! ]0 `6 a" e! D5 Q( B
);6 {9 { g- E$ T* c% w! Z
8 z0 p8 [- r8 q1 m& T) o
// ADD USER PORTS BELOW THIS LINE
7 g$ M8 ]/ f! B; _. Z// -- USER ports added here # m" t: o1 V! f
// ADD USER PORTS ABOVE THIS LINE
3 }8 U. B7 a4 L1 c& ^1 B4 { A$ a) Z+ q+ w
input ACLK;
, \8 {% y+ q, F1 a3 Sinput ARESETN;: A2 E, T8 Y) J0 c2 M3 Z& e3 Y
output S_AXIS_TREADY;* S2 c$ |1 x: n* c
input [31 : 0] S_AXIS_TDATA;
! f6 [. u6 D) R$ N* g" F2 Iinput S_AXIS_TLAST;+ s5 ~- a) G, _# p
input S_AXIS_TVALID;
( W* A/ F r' X3 ~7 ?output M_AXIS_TVALID;
( U0 N% A7 \' ~$ Q+ p1 ]0 ]5 H7 {. Routput [31 : 0] M_AXIS_TDATA;
' x9 H- |3 H" s+ Moutput M_AXIS_TLAST;+ ^$ u5 n, x9 [! ]4 k' a& C
input M_AXIS_TREADY;
6 ]5 Z J9 u* Y. \, G) \7 U) E7 o ?8 e1 j( q. F3 Z/ T2 z
// ADD USER PARAMETERS BELOW THIS LINE % l: \4 G0 N' l
// --USER parameters added here * ?5 @" k# D# p& D0 P; W
// ADD USER PARAMETERS ABOVE THIS LINE0 s R2 `. W& Z& E! D
) G( j( p$ P6 I% q G U
. F& H0 }+ e u7 d- S( ]# v, \, y! n//----------------------------------------' i6 y6 {; ?7 k( Z8 d7 `
// Implementation Section
1 C* k* ?4 B) d, {& ]+ l& b6 y//----------------------------------------
; N* C4 E* t: A, r3 R( h// In this section, we povide an example implementation of MODULE tft_lcd
, I) V# ~7 X9 R. O// that does the following:
4 A: ?% O0 t8 e5 S+ d4 [//7 M+ @; D: a, Y% i8 ]$ A) |
// 1. Read all inputs+ t& W% G& s, a9 D# g
// 2. Add each input to the contents of register 'sum' which( m) u; ]1 z0 U" _2 r: i( l
// acts as an accumulator& B9 }0 Z5 ]1 j! |, N
// 3. After all the inputs have been read, write out the; ?& x7 v- g: t7 z' R
// content of 'sum' into the output stream NUMBER_OF_OUTPUT_WORDS times5 O5 L0 [; H4 q) L3 q& }0 Q
//
6 t7 G9 s: k' ~) |5 ~: b// You will need to modify this example for9 K5 G- U; g& [
// MODULE tft_lcd to implement your coprocessor7 m5 T/ r+ `7 \; @1 _. ]' Q
( m' `; y8 J4 \* N2 j% a" a+ {: Q // Total number of input data.; F# W# {8 s m& Q& T5 q6 r. [# y# I- o! o
localparam NUMBER_OF_INPUT_WORDS = 8;
% x0 k# G- Y+ o, i
& o3 }+ l9 \. C // Total number of output data
" `3 i) k* X/ C1 Z localparam NUMBER_OF_OUTPUT_WORDS = 8;8 c) S3 ?4 b1 I3 g: @! q
4 @% ?$ e. V' k: Y/ Z // Define the states of state machine0 v; s* G! z3 e% i
localparam Idle = 3'b100;
% s& Y5 S6 j5 D4 u0 ~ localparam Read_Inputs = 3'b010; h' G. Z0 c. A; {
localparam Write_Outputs = 3'b001;9 o9 v% l1 O/ \5 Z" T6 v- F
q+ M/ @! ~/ n( m reg [2:0] state;
5 f! Z! n% @4 j" j8 {7 n* l( K/ Q+ W' R! ^4 K
// Accumulator to hold sum of inputs read at any point in time: P. }; y: z, a& q
reg [31:0] sum;
" J5 t6 Z, O# R1 l. `- j# B8 e1 ?4 z# d# L) d7 F. r: W9 B
// Counters to store the number inputs read & outputs written) l+ I4 [6 y3 B' |. u6 n4 K9 e. t
reg [NUMBER_OF_INPUT_WORDS - 1:0] nr_of_reads;
- E9 i \# @( l/ Y! W# E1 ^ reg [NUMBER_OF_OUTPUT_WORDS - 1:0] nr_of_writes;; I8 k! M, k3 k5 {
! R7 z( k4 f% K
// CAUTION:; H; ~( b) r5 ~6 |2 ? G
// The sequence in which data are read in should be
: @7 J5 m+ ^$ A5 p/ f: g // consistent with the sequence they are written in the
9 Y1 L9 m+ p! s8 I // driver's tft_lcd.c file* a! z S. K" j/ w* b8 x5 o
8 C% {5 o: S* @) t7 [- \! r assign S_AXIS_TREADY = (state == Read_Inputs);
/ J* U( }8 c1 N" Z assign M_AXIS_TVALID = (state == Write_Outputs);
4 O4 r9 y9 c2 `6 o V& o& ], o5 \: b7 \, q& D8 T5 Z0 ~
assign M_AXIS_TDATA = sum;3 O7 b# l& b* M2 O* n2 {. I
assign M_AXIS_TLAST = 1'b0;' @0 O# d! }# q- z, b
. j7 {( h+ {2 `4 r
always @(posedge ACLK) + C, ^& }& r; w: C
begin // process The_SW_accelerator
- a) Y* G) h2 h, l if (!ARESETN) // Synchronous reset (active low)$ F. f8 M; n6 z: B
begin5 _8 J y: y J$ O w
// CAUTION: make sure your reset polarity is consistent with the2 C6 C6 d" I$ s0 [1 ^! F
// system reset polarity
& Q! p b. x/ q& P state <= Idle;3 ~/ z* F' d2 ?1 }; P
nr_of_reads <= 0;6 B; d" }" q2 s9 W8 G) ^5 y
nr_of_writes <= 0;: y: g4 l8 J6 ~- s7 H* F$ M
sum <= 0;: N) B% R! S! t' A
end
7 N$ D7 J3 I7 P else0 w+ A. a$ t/ h7 b
case (state)
! k- X, p5 n* h Idle:
. V! m6 Y6 B- g$ [( k, L if (S_AXIS_TVALID == 1)
3 A ?% b/ T: K4 K6 _ begin
, O/ F5 v+ o& A7 K H; F8 B state <= Read_Inputs;/ @7 d: Q f/ q5 V$ w: S! s/ j1 _% X
nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1;
, G) g; S4 J0 ]- |7 ]5 l; C' m sum <= 0;
) h: D) {/ L0 J5 m* L I' S9 p0 q% s end
3 G( f9 x) i" `" j& R( O
4 a. T2 d9 V3 b" Y4 E Read_Inputs:
$ h$ E2 b" j3 B! n4 `5 B; Q if (S_AXIS_TVALID == 1)
: A$ @' m7 f4 ] begin1 i) G: j1 \7 l1 U* t6 `, p1 L
// Coprocessor function (Adding) happens here
5 E7 g2 U9 B( a( O sum <= sum + S_AXIS_TDATA;# n9 ~' E# m. s# K
if (nr_of_reads == 0): Y; x4 a E A. X: d
begin. s& m. ~* J" U# z* p/ T7 N
state <= Write_Outputs;
6 @2 u$ W; u+ o5 N: J5 ~ nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1;. q# O# ?& t. [
end. W* H: o& M+ {* D8 _
else
4 \/ v8 i4 c5 A& c* d nr_of_reads <= nr_of_reads - 1;
5 W9 v+ n! h5 F2 ] end# A$ l1 B, M9 v+ x
* p: D9 E+ o, X! q$ O
Write_Outputs: / | g7 s- @$ f6 u/ B% w$ z
if (M_AXIS_TREADY == 1) 3 L; s( Y1 M& g& s4 q) m0 T, ]" M' U
begin
) i3 [ Q o" j* E! {- Y$ r if (nr_of_writes == 0) % q( q' ~, l" C' I$ M% Y* d0 U
state <= Idle;& O8 Z( y. p- [% y& h( W5 P
else
4 y n9 y: u7 g; F1 |# @9 E nr_of_writes <= nr_of_writes - 1;
" W' ?& _6 s( i! H+ i* W: g' Q end
8 @8 m- a/ [7 I v3 w8 q6 X7 A k endcase
5 _9 A a, r& e% s! t. v/ E. \ end6 O4 ^, G5 D) q& }: a) j4 q, B8 p# \
$ o0 R/ {! e# p$ H) `* _9 h* H" J9 w6 yendmodule
1 S. E0 C; n: k, q# w) I: N% @7 Y% ?2 D4 t6 U
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